1. Field of the Invention
The present invention relates to an analog to digital converter, and, more particularly relates to a flash type analog to digital converter.
2. Description of the Related Art
A flash type analog to digital converter compares analog voltages input to a plurality of comparators and reference voltages obtained from voltage division resistors and converts output signals from these comparators to a digital code by an encoder. FIG. 1 is a view showing an example of the flash type analog to digital converter for converting an analog signal V.sub.in to four bits D3, D2, D1, and D0 of digital signals. As illustrated, 16 resistor elements R16, R15, . . . , and R1 are connected in series between reference voltages V.sub.ref1 and V.sub.ref0. Contacts of these resistor elements are connected to inverted input terminals (-) of 15 comparators C15, C14, . . . , and C1, and the analog signal V.sub.in is connected to the non-inverted input terminals (+) of the comparators C15, C14, . . . , and C1. Output signals of the comparators C15, C14, . . . , and C1 or the inverted signals thereof are individually input to 15 AND gates A15, A14, . . . , and A1. For example, the output signal of the comparator C15 is input to both input terminals of the AND gate A15, while the inverted signal thereof is input to one input terminal of the AND gate A14 and the output signal of the comparator C14 is input to the other input terminal of the AND gate A14.
Output signals of the AND gates A15, A14, . . . , and A1 are input to the encoder ECD. The encoder ECD converts 15 signals input from the AND gates A15, A14, . . . , and A1 to four bits D3, D2, D1, and D0 of digital signals.
Note that the encoder ECD is constituted by a ROM circuit formed on for example a substrate. The ECD part of FIG. 1 is a conceptual view of an operational principle thereof. A double circle in the figure indicates a logical element for finding the OR logic of the signals. For example, as illustrated, the most significant bit (MSB) D3 of the digital signals D3, D2, D1, and D0 is found by the OR logic of the eight output signals of the AND gates A15 to A8. The least significant bit (LSB) D0 is found by the OR logic of the eight output signals of the AND gates A15, A13, A11, A9, A7, A5, A3, and A1.
Namely, the output signals of the AND gates A15 to A1 are converted to binary codes by the illustrated encoder ECD. Further, it is also possible to think of the AND gates A15 to A1 and the encoder ECD together as an encoder. The encoder of this case has a function for converting the 15 output signals of the comparators C15 to C1 to the binary codes.
In the above flash type analog to digital converter, 16 divided reference voltages are generated by the 16 resistor elements R16 to R1 connected in series. These reference voltages are individually input to the inverted input terminals (-) of the comparators C15 to C1. The analog signal V.sub.in is input to the non-inverted input terminals (+) of the comparators C15 to C1. The comparators operate in accordance with the (not illustrated) clock signal, compare the analog signal V.sub.in and the reference voltage at for example the rising edge of the clock signal, and output signals of the high level or low level to the output terminals.
FIG. 2 is a view showing an example of the conversion operation of the analog to digital converter.
In FIG. 2, "H" indicates a state where the signal line is held at a high level, and "L" indicates a state where the signal line is held at a low level. In this example, it is assumed that for example the input analog signal V.sub.in is higher than the reference voltage V.sub.r8 input to the inverted input terminal of the comparator C8 and lower than the reference voltage input to the inverted input terminal of the comparator C9. In this case, the output signals of the comparators C8 to C1 at a high level "H", and the output signals of the comparators C15 to C9 are at a low level "L". Then, signals other than the output signal of the AND gate A8 are all held at the low level. The output signals D3, D2, D1, and D0 of the encoder ECD become "HLLL". This corresponds to for example "1000" of the binary code.
In this way, by the flash type analog to digital converter, a digital code in accordance with the level of the input analog signal V.sub.in is obtained. Namely, the analog signal V.sub.in is converted to a digital signal of the binary code format.
In the above flash type analog to digital converter of the related art, there is a problem of the output after the conversion becoming unstable, i.e., the "meta-stable" problem. Namely, when a difference between the analog signal V.sub.in and the reference voltage of the comparator is small, even if the output signal of the comparator is in the latched state, the output signal level does not completely become the high level or low level and the comparator outputs an intermediate level "M" (hereinafter, referred to as the "M level"), whereby there is a possibility of occurrence of an error in the output code of the encoder. Below, the cause thereof will be explained referring to the circuit diagram of the comparator shown in FIG. 3 and waveform diagrams shown in FIGS. 4 and 5.
FIG. 3 is a view showing an example of a comparator having a latching function. The comparator of the present example is constituted by resistor elements R1 and R2, current sources I1, I2, and I3, and npn transistors Q1 to Q8.
A differential amplifier is constituted by npn transistors Q1, Q2, and Q3. The base of the npn transistor Q1 is connected to the input terminal T.sub.in of the analog signal V.sub.in, and a collector is connected to the supply line of a power supply voltage V.sub.CC via a resistor element R1. The base of the npn transistor Q2 is connected to the input terminal T.sub.ref of the reference voltage V.sub.ref, and the collector is connected to the supply line of the power supply voltage V.sub.CC via a resistor element R2. Contacts of the collectors of these npn transistors and the resistor elements form nodes ND1 and ND2. Emitters of the npn transistors Q1 and Q2 are commonly connected to the collector of the npn transistor Q3.
A latch circuit is constituted by npn transistors Q4. Q5, and Q6. The base of the npn transistor Q4 is connected to the node ND2, the collector is connected to a node ND1, the base of the npn transistor Q5 is connected to the node ND1, and the collector is connected to the node ND2. Emitters of these npn transistors are commonly connected to the collector of the npn transistor Q6.
Further, the base of the npn transistor Q3 is connected to the input terminal T.sub.clkn of the clock signal CLKN, the base of the npn transistor Q6 is connected to the input terminal T.sub.clk of the clock signal CLK, and the emitters of these npn transistors are connected to the current source I1. Here, the clock signal CLKN is the inverted signal of the clock signal CLK.
The output circuit is constituted by npn transistors Q7 and QB and current sources I2 and I3. The base of the npn transistor Q7 is connected to the node ND1, the collector is connected to the supply line of the power supply voltage V.sub.CC, and the emitter is connected to the current source I2. The base of the npn transistor Q8 is connected to the node ND2, the collector is connected to the supply line of the power supply voltage V.sub.CC, and the emitter is connected to the current source 13.
Further, the emitter of the npn transistor QB is connected to the output terminal T.sub.out of the comparator, and the emitter of the npn transistor Q7 is connected to the inverted output terminal T.sub./out of the comparator.
In a semi-cycle where the clock signal CLKN is at a high level, a current i.sub.1 of the current source I1 flows through the collector of the npn transistor Q3, a differential amplifier constituted by the npn transistors Q1 and Q2 operates, and potentials of the collectors of these transistors, that is, the nodes ND1 and ND2, are determined in accordance with the levels of the analog signal V.sub.in and the reference voltage V.sub.ref. For example, when the level of the analog signal V.sub.in is higher than the reference voltage V.sub.ref, the node ND1 is held at the low level and the node ND2 is held at the high level. Further, at this time, the clock signal CLK has become the low level, therefore, a current does not flow through the collector of the npn transistor Q6. and the latch circuit does not operate.
After the clock signal CLKN is switched to the low level, a current does not flow through the collector of the npn transistor Q3, current flows through the collector of the npn transistor Q6, the latch circuit operates, and the potentials of the nodes ND1 and ND2 are held.
In this way, during a period where the clock signal CLKN is at the high level and the clock signal CLK is at the low level, a difference between the analog signal V.sub.in and the reference voltage V.sub.ref is amplified by the differential amplifier and output to the nodes ND1 and ND2. During a period where the clock signal CLKN is at the low level and the clock signal CLK is at the high level, the potentials of the nodes ND 1 and 2 are held by the latch circuit.
The potentials of the nodes ND1 and ND2 are converted in level by the output circuit comprising the npn transistors Q7 and Q8 and the current sources I2 and I3 and then output.
By the above comparator, where the level of the analog signal V.sub.in is higher than the reference voltage V.sub.ref, the output terminal T.sub.out is held at the high level (hereinafter referred to as an "H level"), and the inverted output terminal T.sub./out is held at the low level (hereinafter referred to as an L level). Conversely, where the level of the analog signal V.sub.in is lower than the reference voltage V.sub.ref, the output terminal T.sub.out is held at the L level and the inverted output terminal T.sub./out is held at the H level,
FIG. 4 is a view showing waveforms of the clock signal CLK, analog signal V.sub.in, reference voltage V.sub.ref, and output signals V.sub.out, and V.sub./out of the comparator.
When the level difference between the analog signal V.sub.in and the reference voltage V.sub.ref is small, even in the latch mode when the clock signal CLK is at the high level, the output signal is not completely set at the H level or the L level, and the signal of M level is sometimes output to the output terminal T.sub.out and the inverted output terminal T.sub./out of the comparator. The waveform diagram of FIG. 5 shows such a state.
The output signal of M level of the comparator is similarly output as the M level to the encoder ECD via the AND gate of the latter stage. Among the output signals D3, D2, D1, and D0 of the encoder ECD, a bit which is output while being held at the M level as it is is produced. The M level is finally recognized to be either of the H level or the L level. There arises a possibility of malfunction of the analog to digital converter because of the M level signal.
Here, assume that the level of for example the input analog signal V.sub.in is almost the same as the level of the reference voltage V.sub.r8 input to the inverted input terminal (-) of the comparator C8. At this time, the signal of the M level is output to the output terminal of the comparator C8, and the output signals of both of the AND gates A8 and A7 are set to the M level in accordance with this. Below, an explanation will be made of four modes wherein output signals "MM" of the AND gates A8 and A7 are respectively recognized to be "HH" "HL", "LH", and "LL".
FIGS. 6 to 9 are views showing the states of the output signal of the encoder ECD in the four modes mentioned above.
As shown in FIG. 6, the output signals of the AND gates A8 and A7 are recognized to be "HH". The output of the encoder ECD becomes "HHHH" according to this. This corresponds to the case where the level of the analog signal V.sub.in exceeds the level of the reference voltage V.sub.r15 input to the comparator C15 and therefore an error occurred in the conversion result.
In the case of FIG. 7, the output signals of the AND gates A8 and A7 are recognized to be "HL", the output of the encoder ECD becomes "HLLL" according to this, and this is recognized as the normal conversion result.
In the case of FIG. 8, the output signals of the AND gates A8 and A7 are recognized to be "LH", the output of the encoder ECD becomes "LHHH" according to this, and this is recognized too as the normal conversion result.
On the other hand, as shown in FIG. 9, the output signals of the AND gates A8 and A7 are recognized to be "LL", the output of the encoder ECD becomes "LLLL" according to this. This corresponds to the case where the level of the analog signal V.sub.in is not more than the level of the reference voltage V.sub.r1 input to the comparator C1 and an error occurs in the conversion result.
As mentioned above, when the signal of the "MM" level is output to the AND gates A8 and A7, when the output signals are recognized as "HH" or "LL", the analog to digital converter malfunctions. In order to solve this, in the analog to digital converter of the related art, there is a method of setting the latch mode time large until the output signal level of the comparator is sufficiently defined to either of "H" or "L", thereby eliminating the M level of the output signal and preventing a malfunction, but it has a defect of a reduction of the operation speed of the analog to digital converter.